1. Field of the Invention
The present invention relates to special purpose microprocessors, and more particularly to a microprocessor adapted for use in controlling sequential devices.
2. Description of the Prior Art
One of the more recognized features of conventional microprocessors is their adaptability for use as logic devices. By proper coding a set of instruction sequences can logically control any device heretofore controlled by complex switching systems. With the decreasing cost of semiconductor chips and particularly the decreasing costs of fixed memory the use of microprocessors for this function has experienced wider acceptance. A typical microprocessor used as the control system in a mechanized device receives a plurality of binary inputs indicating the position of switches set by the operator, timer inputs and inputs describing the various states of the machine itself as it progresses through the selected sequence. The output is again typically binary providing the control signals to mechanisms like motors, clutches, brakes, or other devices. Generally, however, the structure of a microprocessor is configured for broad applications and for that reason logic elements unnecessary for control are included. In this broad form relatively complex instruction sequences are necessary and any control will necessarily entail considerable programming cost. Specifically it is the erasable memory in conjunction with the arithmetic logic unit (ALU) that heretofore has been at the heart of the logical sequences. The execution of a large instruction set through this arithmetic logic unit and with the aid of erasable memory is the primary source in the increased program complexity and, furthermore, the training level for the operator.
Sequential devices, in particular, operate on relatively straightforward logical decisions and the breadth of a typical microprocessor is therefore substantially excessive for these purposes. Furthermore, with the use of a read only memory (ROM) storing several well selected instructions no operation in the ALU is necessary, most of the logical decisions being capable of implementation in a few simple gates.